1. Field of the Invention
The present invention relates to a semiconductor device with an insulated gate field effect transistor and a method of making the same.
2. Description of the Prior Art
Heretofore, there have been proposed a variety of semiconductor devices provided with an insulating gate field effect transistor (hereinafter referred to as an MIS (Metal-Insulator-Semiconductor) FET). The MIS FET is divided into a surface channel type and a bulk channel type.
The surface channel type MIS FET basically has a structure which comprises a semiconductor substrate of a first conductivity type, first and second semiconductor regions of a second conductivity type reverse from the first one and formed in the semiconductor substrate from the side of its major surface, an insulating layer formed on the major surface of the semiconductor substrate to extend over a region between the first and second semiconductor regions, and a conductive layer formed on the insulating layer in opposing relation to that region of the semiconductor substrate defined between the first and second semiconductor regions. In such a surface channel type MIS FET, the first and second semiconductor regions serves as the one and the other of source and drain regions, respectively; the region of the semiconductor substrate defined between the first and second semiconductor regions serves as a channel forming region; that region of the conductive layer confronting the channel forming region serves as a gate electrode; and that region of the insulating layer underlying the gate electrode serves as a gate insulating layer. With the arrangement of the surface channel type MIS FET described above, the ON or OFF state is obtained between the source and drain regions in accordance with a control voltage which is applied across the source region and the gate electrode. The ON or OFF state is dependent on whether or not an inversion layer, that is, a channel is formed in the surface of the channel forming region.
The bulk channel type MIS FET basically has a structure which comprises, by way of example, a semiconductor substrate of a first conductivity type, first and second semiconductor regions of a second conductivity type opposite to the first one and formed in the semiconductor substrate from the side of its major surface, a third semiconductor region formed in the semiconductor substrate from the side of its major surface to extend between the first and second semiconductor regions and having a lower impurity concentration than the first and second semiconductor regions, an insulating layer formed on the third semiconductor region, and a conductive layer formed on the insulating layer in opposing relation to the third semiconductor region. In such a bulk channel type MIS FET, the first and second semiconductor regions serve as the one and the other of source and drain regions, respectively, as in the case of the surface channel type MIS FET; the third semiconductor region serves as a channel forming region; that region of the conductive layer confronting the channel forming region serves as a gate electrode; and that region of the insulating layer underlying the gate electrode serves as a gate insulating layer. With the arrangement of the bulk channel type MIS FET described above, an ON or OFF state is obtained between the source and drain regions in accordance with a control voltage which is applied across the source and drain regions as is the case with the surface channel type MIS FET. This ON or OFF state depends on whether or not a depletion layer formed in the channel forming layer to spread from the side of the gate insulating layer towards the semiconductor subtrate reaches the latter.
In either of the surface channel and bulk channel type MIS FETs, it is desirable for a high-speed operation and the reduction of the overall dimensions to decrease the inner spacing of the source and drain regions, thereby to minimize the length of the gate electrode correspondingly.
In the conventional MIS FETs, however, there is a certain limitation on reducing the length of the gate electrode to less than 1 .mu.m. The reason is as follows: The gate electrode is usually formed by the photoetching method employing a mask. With the photoetching method, it is very difficult to form the gate electrode of a length smaller than its thickness. The length of an ordinary gate electrode is twice to five times larger than its thickness. Accordingly, by forming the gate electrode to a thickness 1/2 to 1/5 times as large as its length through utilization of the photoetching method, the length of the gate electrode can be reduced smaller than 1 .mu.m. In such a case however, the gate electrode becomes as thin as 1/2 to 1/5 .mu.m, resulting in a large resistance, which is an obstacle to high-speed operations. Thus the prior art has impsoed a certain limitation on reducing the length of the gate electrode down to less than 1 .mu.m.
Consequently, the prior art MIS FETs have the defect of some limitations on speeding up their operations and reducing their areas.